The present invention relates to methods and apparatus for achieving multiple processing configurations using a multi-processor system architecture.
In recent years, there has been an insatiable desire for faster computer processing data throughputs because cutting-edge computer applications involve real-time, multimedia functionality. Graphics applications are among those that place the highest demands on a processing system because they require such vast numbers of data accesses, data computations, and data manipulations in relatively short periods of time to achieve desirable visual results. These applications require extremely fast processing speeds, such as many thousands of megabits of data per second. While some processing systems employ a single processor to achieve fast processing speeds, others are implemented utilizing multi-processor architectures. In multi-processor systems, a plurality of sub-processors can operate in parallel (or at least in concert) to achieve desired processing results.
Some multiprocessing systems contemplate interconnections via interfaces in a matrix configuration to improve processing throughput and versatility. Examples of such configurations are disclosed in U.S. Patent Publication No.: 2005/0097231 and U.S. Pat. No. 6,526,491, the entire disclosures of which are hereby incorporated by reference. While the techniques disclosed in these documents may be useful in various applications, they may not provide the level of flexibility and/or programmability desirable in other applications.
Accordingly, there are needs in the art for new methods and apparatus for interconnecting one or more multiprocessor systems with one or more external devices to achieve higher processing capabilities.